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YTD428
APPLICATION MANUAL
IDSU
ISDN DSU for Terminal Equipment
YTD428 APPLICATION MANUAL CATALOG No.: LSI-6TD428A32 2005.1
CONTENTS
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Contents
1. INTRODUCTION ..................................................................................... 2
1.1 Features ................................................................................................................................ 3
2. BLOCK DIAGRAM .................................................................................. 4
2.1 Internal Block Diagram .......................................................................................................... 4 2.2 DSU Configuration Example ................................................................................................. 5
3. PIN DESCRIPTIONS .............................................................................. 7
3.1 Pin Assignments .................................................................................................................... 7 3.2 Pin Functions ........................................................................................................................ 8
4. DETAILS OF FUNCTIONS.................................................................... 13
4.1 U Reference Point Section .................................................................................................. 13 4.2 Circuit Termination / Line Termination Section .................................................................... 13 4.3 Interface Switch Section ...................................................................................................... 14 4.4 T Reference Interface Section ............................................................................................ 15
5. ELECTRICAL CHARACTERISTICS ..................................................... 16
5.1 Absolute Maximum Ratings ................................................................................................. 16 5.2 Recommended Operating Conditions ................................................................................. 16 5.3 DC Characteristics .............................................................................................................. 17 5.4 AC Characteristics ............................................................................................................... 18
6. PIN DESCRIPTIONS ............................................................................ 22 REFERENCE CIRCUIT ............................................................................ 23
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INTRODUCTION
1. INTRODUCTION
YTD428 is a LSI which provides the ISDN subscriber interface (two-wire time compression multiplexing operation) and the NT side of the ISDN Basic Rate user-network interface function (digital four-wire time-division full-duplex operation). It is capable of providing the electric characteristics conforming to TTC Standard JT-I430 and JT-G961. YTD428 incorporates the circuit termination and line termination functions on a single chip allowing the user to easily configure a DSU (Digital Service Unit) that consumes small amount of power at a minimal cost. In addition, a TTL interface is provided at the T reference point (layer 1 level). This feature is especially effective when combined with YAMAHA's ISDN LSI for S/T reference point interface, YTD423 or YTD418. It allows considerable cost reduction on parts around the pulse transformer when constructing a device with a built-in DSU. The driver/receiver section of the T reference point interface can be separated from the DSU section and be used independently. The user can enable or disable this feature as necessary.
INTRODUCTION
-3-
1.1 Features
s Circuit Termination Section
s
q
Conforms to TTC Standard JT-I430 and JT-G961
Digital four-wire time-division full-duplex operation q Two-wire time compression multiplexing operation Transmission rate at U reference point: 320 kbit/s, at T reference point: 192 kbit/s q Frame assembling and disassembling function
q q q q
State transition control Loopback function T reference point timing control (switch between short passive bus / extended passive bus, point-to-point) U reference point driver control
q
s Line Termination Section
s
q q
Conforms to TTC Standard JT-G961
f equalizer
Bridged tap equalizer
s T Reference Point Interface Section
q
The T reference point driver / receiver section can be separated from DSU section, and use independently (TE mode). The user can enable or disable this feature as necessary.
s Others
q q
+5 V single power supply
Low power consumption q 100 pin SQFP
-4-
BLOCK DIAGRAM
2. BLOCK DIAGRAM
2.1 Internal Block Diagram
YTD428
U ref. pt. I/F section Variable Amplifier ADC Peak hold
T ref. pt. I/F section
CT/LT section CT block Interface switch section
T ref. pt. driver
T ref. pt. receiver
LT block
U ref. pt. driver control
TTL I/F
S/T ref. pt. LSI YTD418 or YTD423
CT : Circuit Termination LT : Line Termination
U ref. pt. side
T ref. pt. side
BLOCK DIAGRAM
-5-
2.2 DSU Configuration Example
YTD428 incorporates the circuit termination, line termination, T reference point interface and U reference point interface functions on a single chip allowing the user to easily configure a DSU that consumes small amount of power at a minimal cost. The user can select from the two types of configurations. One is the general configuration in which a transformer is used at the T reference point interface. The other is a configuration in which a TTL interface is used to directly connect to the T reference point LSI. s Configuration example of a general DSU
Various functions are incorporated on a single chip allowing the user to create a low power-consuming product at a low cost.
Layer 3 info. Bch data
T ref. pt.
included driver/receiver for S/T ref. pt.
TA / TB L2 U ref. pt. driver Call control circuit
U ref. pt. side
YM7405 or YTD410 for S/T ref. pt.
RA / RB
DSU
YTD428
L1
-6-
BLOCK DIAGRAM
s Configuration example of a device with a built-in DSU that uses an I.430 TTL interface at the T ref. pt.
When using YTD428 with YAMAHA'S S/T reference point interface LSI to create a device with a built-in DSU, they can be connected directly through the I.430 TTL interface. This results in a reduction of pulse transformer parts.
T ref. pt. side (to terminal)
YTD428
RA / RB
DSU section
U ref. pt. I/F
TA / TB
L2
U ref. pt. driver
Call control circuit
I.430 TTL I/F (No transformer is requied)
YTD418 or YTD423
Layer 3 information (Bch data)
s Example of using T reference point driver / receiver section independently
By setting the Interface switch, the drive / receiver of the T reference point interface section can be separated from the circuit termination (CT) and line termination (LT) section and be used independently. The user can enable or disable this feature as necessary.
T ref. pt. side (DSU)
YTD428
RA / RB T ref. pt. I/F TA / TB I/F switch CT and LT U ref. pt. I/F
DSU section
L2 U ref. pt. driver Call control circuit TTL I/F (No transformer is required)
YTD418 or YTD423
Layer 3 information (Bch data)
U ref. pt. side
L1
U ref. pt. side
T ref. pt. I/F
I/F switch
CT and LT
L1
PIN DESCRIPTIONS
-7-
3. PIN DESCRIPTIONS
3.1 Pin Assignments
DVDD TEST3 TEST2 TEST1 TEST0 LPSEL LOCAL DVSS RESET POWMON REV NTSEL MULTI TSMPAUT TSMPSEL ODSEL RDP TDP CLK192K DVDD LTD HTD LRD HRD DVSS
TEST4 TEST5 TEST6 TEST7 LOOP2A LPSW TEST8 DVSS CLK1536 DVDD CLK4K CLK256K CLK200 CLK400 DVSS EXID TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 DVDD TEST16
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
TEST17 TEST18 TEST19 TEST20 TEST21 TEST22 CLKSEL DVSS UDM0 UDM1 UDP0 UDP1 DVDD TEST23 TEST24 TEST25 TEST26 TEST27 TEST28 DVSS AVSS1 VRB VRT AVDD1 ATEI
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
YTD428-S 100pin SQFP
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AVSS2 RX LO2 AVDD2 LO1 CX1 AVDD2 LI2 CX2 LICT LI1 AVSS2 AVSS1 SXA SGBP SGB RXS AVDD1 SGA RUC RXU2 SGR AVSS1 RXU1 ATEO
-8-
PIN DESCRIPTIONS
3.2 Pin Functions
s Common Section
Pin No. 3, 13, 96 14, 25 26, 43, 58, 65, 83, 95 8, 99 19, 22 31, 50, 60 74, 88 59 41 Pin Name AVSS1 AVSS2 DVSS AVDD1 AVDD2 DVDD CLK1536 POWMON I/O GND GND GND PWR PWR PWR IN IN Analog ground 1 (U ref. pt.) Analog ground 2 (T ref. pt.) Digital ground +5 V 5 % analog power supply 1 (U ref. pt.) +5 V 5 % analog power supply 2 (T ref. pt.) +5 V 5 % digital power supply System clock (15.36 MHz 50 ppm or less) Power supply monitor of the equipment on the T ref. pt. side "H": Power supply OFF "L": Power supply ON Haerdware reset Apply the reset pulse for 1 ms or more after the clock oscillation to operate hardware reset. If the pulse is less than 1 ms, the operation is unpredictable. Hardware reset is required when all following conditions are met. 1. operated by local power 2. LPSEL = "H" 3. U ref. pt. polarity is positive. Function Remarks
42
RESET
IN
Note
Connect input pins that are not normally used to the power supply pin or ground pin. In the same fashion, do not leave pins with pull-up resistor open. Connect them to the power supply pin or ground pin.
PIN DESCRIPTIONS
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s Mode Setting Section
Pin No. 33 Pin Name TDP I/O IN HTD, LTD pulse polarity setting "H": positive polarity "L": negative polarity HRD, LRD pulse polarity setting "H": positive polarity "L": negative polarity T ref. pt. transmit signal setting "H": HRD, LRD pins normal output "L": HRD, LRD pins open drain Function Remarks with pull-up resistor with pull-up resistor with pull-up resistor
34
RDP
IN
35
ODSEL
IN
36
TSMPSEL
IN
T ref. pt. receive data sampling timing setting "H": fixed timing (short passive bus) with pull-up When T ref. pt. data sampling mode is set to "automatic" (TSMPAUT = "L"), resistor set this pin to "H". "L": adaptive timing (point-to-point connection, extended passive bus) T ref. pt. data sampling mode setting "H": manual setting (TSMPSEL pin state is valid) "L": automatic setting (set TSMPSEL pin to "H") T ref. pt. multiframe support setting "H": support multiframe "L": do not support multiframe T ref. pt. mode setting "H": NT mode "L": TE mode (T ref. pt. I/F block operates independently of DSU block) Power feeding mode setting "H": phantom power feeding mode "L": local power fedding mode LPSW signal setting "H": call only extended loopback 2A "L": normal call, call by extended loopback 2A (loop control signal at local power feeding mode) Loopback setting "H": transmit ID1 = "1" (correspond to extended loopback 2) "L": transmit ID1 = "0" (loopback 2A operates at AP = "1") Clock output setting "H": do not output clock "L": output clock with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor
37
TSMPAUT
IN
38
MULTI
IN
39
NTSEL
IN
44
LOCAL
IN
45
LPSEL
IN
with pull-up resistor
66
EXID
IN
with pull-up resistor with pull-up resistor
82
CLKSEL
IN
Note 1
When not using TTL interface, set HTD, LTD pins as bellow. When TDP = "H", set HTD, LTD = "L" When TDP = "L", set HTD, LTD = "H"
Note 2
When using the YTD428 on a terminal with built-in DSU, it is recommended that fixed timing be selected for the sample timing of T reference point receive data (TSMPSEL="H" and TSMPAUT="H"). This is because the bus distribution form becomes a short passive bus in this case.
Note 3
When using NTSEL, external terminating resistor setting is required. When NTSEL = "H", terminating resistor is required. When NTSEL = "L", remove terminating resistor as necessary.
Note 4
Set LOCAL = "L" when LPSEL = "L" or CLKSEL = "L".
- 10 -
PIN DESCRIPTIONS
s T Reference Point Section
Pin No. 15 16 17 18 20 21 23 24
Note 1
Pin Name LI1 LICT CX2 LI2 CX1 LO1 LO2 RX
I /O IN OUT IN OUT OUT S/T line input S/T line reference source output
Function
Remarks
Connecting external capacitor and resistor 0.1 F capacitor and 1 M resistor are to be connected across the CX2 pin and the AVSS2 pin. S/T line input Connecting external capacitor 22 F capacitor is to be connected across the CX1 pin and the AVSS2 pin. S/T line output S/T line output Connecting external resistor 33 k resistor is to be connected across the RX pin and the AVSS2 pin .
When not using T ref. pt. analog interface, set these pins as bellow. The LI1, LI2 and LICT pins are to be connected each other (short). 0.1 F capacitor is to be connected across the LICT pin and the AVSS2 pin.
Note 2
About how to connect external capacitor and resistor, refer to "REFERENCE CIRCUIT" .
Pin No. 27 28 29 30
Note
Pin Name HRD LRD HTD LTD
I/O OUT OUT IN IN
Function NTSEL = "H": DSU transmit data (+) NTSEL = "L": TE receive data (+) NTSEL = "H": DSU transmit data (--) NTSEL = "L": TE receive data (--) NTSEL = "H": DSU receive data (+) NTSEL = "L": TE transmit data (+) NTSEL = "H": DSU receive data (--) NTSEL = "L": TE transmit data (--)
Remarks
When not using TTL interface, set HTD, LTD pins as bellow. When TDP = "H", set HTD, LTD = "L" When TDP = "L", set HTD, LTD = "H"
PIN DESCRIPTIONS
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s U Reference Point Section
Pin No. 2 4 5 6 7 9 10 11 12 97 98 Pin Name RXU1 SGR RXU2 RUC SGA RXS SGB SGBP SXA VRB VRT I/O IN OUT IN OUT OUT Receive signal input 1 Analog signal reference output Receive signal input 2 0.1 F capacitor is to be connected across the RUC pin and the AVSS1 pin. 0.0047 F (10%) capacitor is to be connected across the SGA pin and the SGR pin. 0.0022 F (10%) capacitor is to be connected across the RXS pin and the SGR pin. 0.015 F (10%) capacitor is to be connected across the SGB pin and the SGR pin. 0.15 F (10%) capacitor is to be connected across the SGBP pin and the SGR pin. This pin must be left unconnected. ADC reference power supply (low voltage) 0.1 F capacitor is to be connected across the VRB pin and the AVSS1 pin. ADC reference power supply (high voltage) 0.1 F capacitor is to be connected across the VRT pin and the AVSS1 pin. Function Remarks
Pin No. 84 85 86 87
Pin Name UDM0 UDM1 UDP0 UDP1
I/O OUT OUT OUT OUT Negative pulse driving signal Negative pulse driving signal Positive pulse driving signal Positive pulse driving signal
Function
Remarks
Pin No.
Pin Name
I/O
Function U ref. pt. polarity When LPSEL = "H", set this pin to "H". When LPSEL = "L", set this pin as bellow. "L": positive polarity "H": reverse polatity "L": normal operation "H": indicating loopbak 2 Call control signal "L": normal operation "H": call initiate request
Remarks
40
REV
IN
55
LOOP2A
OUT
56
LPSW
OUT
- 12 -
PIN DESCRIPTIONS
s Clock Output Pins
Pin No. 32 61 62 63 64
Note 1
Pin Name CLK192K CLK4K CLK256K CLK200 CLK400
I /O OUT OUT OUT OUT OUT
Function 192 kHz clock (usually fixed to "L") Output clock when CLKSEL = "L" and LOCAL = "L". 4 kHz clock (usually fixed to "L") Output clock when CLKSEL = "L" and LOCAL = "L". 256 kHz clock (usually fixed to "L") Output clock when CLKSEL = "L" and LOCAL = "L". 200 Hz clock (usually fixed to "L") Output clock when CLKSEL = "L". 400 Hz clock (usually fixed to "L") Output clock when CLKSEL = "L".
Remarks Note 1, 2 Note 1, 2 Note 1 Note 1, 2 Note 1, 2
Outputs "L" when the YTD428 is set to not output the clock. In addition, if the YTD428 is not synchronized to the network, the frequency of the output clock is not guaranteed.
Note 2
Clock is output when REV = "H."
s Test Pins
These are for LSI examinations, and not used in normal operation. Be sure that each pin is set as bellow.
Pin No. 46, 48, 49, 51 ~ 54, 57, 67, 80, 81 89, 91 ~ 93 94 47, 75 ~ 78 68, 69, 90 70 ~ 73 79 100 1 Pin Name TEST0, 2 ~ 9, 21, 22 TEST 23, 25 ~ 27 TEST28 TEST1, 16 ~ 19 TEST10, 11, 24 TEST 12 ~ 15 TEST20 ATEI ATEO I/O Test pin Usually fixed to "H". Test pin Usually fixed to "L". Test pin Usually fixed to "H". Test pin Usually pull up to "H". Test pin Usually pull up to "H". Test pin Usually fixed to "L". Test pin This pin must be left unconnected. Test pin Usually fixed to "L". Test pin Usually pulled up to "H". with pull-up resistor Function Remarks with pull-up resistor
IN
IN IN I/O I/O I/O OUT IN I/O
DETAILS OF FUNCTIONS
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4. DETAILS OF FUNCTIONS
4.1 U Reference Point Section
s Variable Amplifier
This block amplifies the receive signal amplitude to the maximum dynamic range.
s ADC
This block makes an A/D conversion of the received signal and transfers it to the line termination block.
s Peak Hold
This block is performed during the initial training so that the gain of the Variable amplifier block is set to make best communication condition.
4.2 Circuit Termination / Line Termination Section
s Circuit Termination Block
The following functions provide the necessary functions for TTC Standard JT-G961 (TCM operation) and the NT function described in TTC Standard JT-I430. q Rate adaptation and frame assembly / disassembly at the U and T reference points State transition control q U reference point drive control
q
T reference point receive timing control q Loopback control
q
YTD428 supports loopback 2 and loopback C for testing and maintenance. These loopback tests are under local switch control.
s Line Termination Block
The line termination provides the f equalization which compensates the DLL (Digital Local Line) loss and the amplitude distortion, and the BT equalization which compensates the waveform distortion caused by the bridged tap.
- 14 -
DETAILS OF FUNCTIONS
4.3 Interface Switch Section
Normally, this section connects T I/F section with CT/LT section to provide DSU function (NTSEL = "H"). By setting this section, the driver/receiver function of the T I/F section can be separated from the CT/LT section and be used independently (NTSEL = "L"). For example, it is useful under such a situation that there are some terminals which have DSU function on the same S/T line.
T ref. pt. side (DSU)
YTD428
RA / RB T ref. pt. I/F TA / TB I/F switch CT and LT U ref. pt. I/F
DSU section
L2 U ref. pt. driver Call control circuit TTL I/F (No transformer is required)
YTD418 or YTD423
Layer 3 information (Bch data)
Figure 4.1 Image Of Using T Ref. Pt. I/F Drive/Receiver Independently
In case of using NTSEL = "L" (TE mode), the signals of TA/TB and RA/RB should be reversed by switches or other devices. Because S/T bus signals that are connected to TA, TB, RA and RB pin are different between using YTD428 as DSU (NTSEL = "H") and S/T terminal (NTSEL = "L"). Generally speaking, the terminal resistors are only mounted on the nearest terminal from DSU and other terminals that are connected with the same bus don't require the terminal resistors. Therefore, it is useful that switches which can control ON/OFF of the terminal resistors are provided on the equipment.
U ref. pt. side
L1
DETAILS OF FUNCTIONS
- 15 -
4.4 T Reference Interface Section
s Reference Power Supply Block
This block provides the electric power to supply for the receiver block and the driver block.
s Receiver Block
The receiver block receives signal from the S/T bus through the external pulse transformer and converts it to the logic level signal. The voltage threshold level for he receiver is properly adapted automatically according to the receiving signal level.
I.430 receive signal (RA/RB) HRD pin (TTL level) LRD pin (TTL level)
+0 -0
192kHz (AMI)
(NRZ)
(NRZ)
Figure 4.2 Receive Signal Logic (RDP = "H", NTSEL = "L") s Driver Block
The driver block drives the 2:1 turn ratio transformer according to the logic level transmitting signal.
HTD pin (TTL level) LTD pin (TTL level)
(NRZ)
(NRZ)
+0 I.430 transmit signal (TA/TB) -0
192kHz (AMI)
Figure 4.3 Transmit Signal Logic (TDP = "H", NTSEL = "L")
- 16 -
ELECTRICAL CHARACTERISTICS
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Storage Temperature Symbol VDD VI Tstg Min. VSS - 0.3 VSS - 0.3 - 50 Max VSS + 7.0 VDD + 0.3 + 125 Units V V C
5.2 Recommended Operating Conditions
Parameter Supply Voltage Operating Temperature Symbol VDD Top Range 5.0 V 5 % -20 ~ +70 C
ELECTRICAL CHARACTERISTICS
- 17 -
5.3 DC Characteristics
(DVDD = AVDD = 5 .0V, DVSS = AVSS = 0.0 V, Operating Temperature: Top = 25 C)
Parameter Analog Output Allowable Load Impedance Analog Receive Buffer Input Impedance Analog Signal Reference Voltage ADC
Note 1 Note 2 Note 3 Note 4 Note 5
Symbol ZO Zi1 VSG VRT V RB
Condition Note 1 Note 2 Note 3 Note 4 Note 5
Min. 30 10 2.45 0.7AVDD - 0.1 0.3AVDD - 0.1
Typ.
Max.
Units k M
2.50 0.7AVDD 0.3AVDD
2.55 0.7AVDD + 0.1 0.3AVDD + 0.1
V V V
Self-Bias VRT Self-Bias VRB
With respect to SGR, SXA pins. With respect to RXU1 and RXU2 pins. Set SGR pin to open. With respect to VRT pin. With respect to VRB pin.
(DVDD = AVDD = 5.0 5% V, Top = -20 ~ 70 C)
Parameter High Level Input Voltage (TTL) Symbol VIH VIH VIL VIL VIH VIL VOH Condition (Note 1) (Note 2) (Note 1) (Note 2) (Note 3) (Note 3) (Note 4) (Note 5) (Note 4) (Note 5) (Note 6) -10 -10 (Note 7) 36 DVDD - 1.0 DVDD - 1.0 DVSS + 0.4 DVSS + 0.4 DVSS + 0.4 10 10 3.5 1.0 Min. 2.2 3.0 0.8 0.8 Typ. Max. Units V V V V V V V V V V V A A mA
Low level Input Voltage (TTL) High Level Input Voltage (CMOS) Low Level Input Voltage (COMS) High Level Output Voltage (TTL)
Low Level Output Voltage (TTL) Low Level Output Voltage (Open-D) Leak Current Idle Condition Leak Current Power Supply Current
VOL VOL IL ILZ IDD
Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 7
With respect to the digital pins other than RESET, POWDET, CLK1536 and TEST23 ~ 28 pins With respect to RESET, POWDET pins With respect to CLK1536, TEST23 ~ 28 pins With respect to the pin other than HRD, LRD pins Test condition: Output Current "H" level (IOH) = -0.2 mA, Output Current "L" level (IOL) = 1.2 mA With respect to HRD, LRD pins (when ODSEL = "H"), Test condition: IOH = -0.2 mA, IOL = 1.2 mA With respect to HRD, LRD pins (when ODSEL = "L"), When using T ref. pt. analog interface Test condition: IOL = 1.2 mA
- 18 -
ELECTRICAL CHARACTERISTICS
5.4 AC Characteristics
s T Reference Point Receive Characteristic (NT mode)
(VDD = 5.0 5% V , Top = -20 ~ 70 C, Load Capacity: CL = 50 pF)
Parameter Transmit Pulse Width Receive Pulse Width Rise Time Fall Time Phase Diffierence between Tx and Rx signals Phase Difference between Rx signals
Note 1 Note 2 Note 3
Symbol tTPW tRPW tPR tPF tTRD tTRD tPH
Condition
Min. 5.00
Typ. 5.208 5.208
Max. 5.40
Units s s
260 30 Note 1 Note 2 Note 2, Note 3 10.0 10.0 14.0 42.0 2.0
ns ns s s s
With respect to using the Fixed timing With respect to using the Adaptive timing This value shows the difference between two terminals which are connected with bus system.
t TPW HRD
2.0 V
F
0.8 V
t TPW
2.0 V
LRD
L
Transmit data slot
0.8 V
t RPW HTD t RPW
t TRD
F
t FD
Receive data slot 2.4 V 0.4 V
2.4 V
LTD t PR
L
0.4 V
t PF
HTD/LTD (closest terminal) Note 1 HTD/LTD (farthest terminal) Note 2
t PH
Note 1 Note 2
Indicates the terminal that is connected closest from the DSU. The signal from this terminal reaches the DSU the fastest. Indicates the terminal that is connected farthest from the DSU. The signal from this terminal reaches the DSU the slowest.
Figure 5.1 Timing At T Ref. Pt. Interface
ELECTRICAL CHARACTERISTICS
- 19 -
s T Reference Point Receive Characteristic (TE mode)
(VDD = 5.0 5% V, Top = -20 ~ 70 C, CL = 50 pF)
Parameter Symbol tRDR Delay Time tRDL tRDH tRDF Rise Time Fall Time Note 1 Note 2 Note 3 tRR tRF Note 1 Note 2 Condition Min. Typ. Max. 700 200 700 700 30 30 Units ns ns ns ns ns ns
With respect to HRD, LRD pins (ODSEL = "H") With respect to HRD, LRD pins Figure 5.2 shows the timing when RDP = "H". When RDP = "L", the output signal polarity from HRD and LRD pins are inverted.
Receive signal (I) (LI1 - LI2) t RDR t RR HRD (O) t RDH t RR LRD (O) t RDF t RF t RDL t RF
0V
2.0V 0.8 V
2.0 V 0.8 V
Figure 5.2 Receive Timing
- 20 -
ELECTRICAL CHARACTERISTICS
I T Reference Point Transmit Characteristic (TE mode)
(VDD = 5.0 5% V, Top = -20 ~ 70 C, CL = 50 pF)
Pa rameter HTD, LTD Pulse Period HTD, LTD Pulse Gap HTD, LTD Rise Time HTD, LTD Fall Time Symbol
tSW tG AP tSR tSF
Co ndition
Mi n. 4.95 0
Typ.
Max. 5.45 260 260 30
Units s ns ns ns ns ns ns ns ns
tSRL Transmit Signal Delay Time tSRH tSFH tSFL Ze ro Cross Delay Time
tSDZ
Note 1 Note 1 Note 1 Note 1 Note 1
490 1010 165 685 1010
Note 1 Note 2
Measuring with RL voltage drop as shown in Figure 5.4 Figure 5.3 shows the timing when TDP = "H". When TDP = "L", the output signal polarity from HRD and LRD pins are inverted.
t SW HTD (I) t SR LTD (I) t SRH t SRL Transmit signal (O) (LOI - LO2) t SFL t SFH t SR t SRH t SRL t SF t SDZ t SFL t SFH
1.35 V 0.15 V -0.15 V -1.35 V 2.4 V 0.4 V
t SF
t SW
t GAP
2.4 V 0.4 V
Figure 5.3 Transmit Timing
ELECTRICAL CHARACTERISTICS
- 21 -
100 HTD LO1 RO
YTD428
LTD LO2
RL 200
Transmit signal
Figure 5.4 Transmit Block Test Circuit s Driver, Receiver I/O Impedance
Parameters Receiver Input Impedance Driver Ouput Impedance Driver Ouput Impedance
Note 1 Note 2 When no pulse is output. When pulse is output.
Symbol ZLI ZLO1 ZLO0
Condition LI1 - LI2 LO1 - LO2 (Note1) LO1 - LO2 (Note2)
Min. 50 50
Typ.
Max.
Units k k
15
- 22 -
PIN DESCRIPTIONS
6. PIN DESCRIPTIONS
REFERENCE CIRCUIT
- 23 -
REFERENCE CIRCUIT
The reference circuit using YTD428 is shown as bellow.
1S953
12
YTD428
R(1%)
LO1
1
1
R(1%)
LO2 LI1
8.2k
UDM1 UDP1
A1
2SJ278
A1
2SJ278
TDK NL322522T-3R3J
LI2
8.2k
8(1%)
8(1%)
UDP0 2SK2315 UDM0
2SK2315
RA
100
A2
LICT
0.1
33k 22 0.1
1M
A1
0.01(10%) 6
A1
1 2 3 4
15(1W)
L2
KP15N14
RB TA
RX CX1 CX2
5
560(1%)
RXU2
1.8k(1%) 1.8k(1%)
8 7
FG
1/160V VRYA15 15(1W)
KP4N12
KP15N14
RXU1
A2
100
560(1%)
L1
TDK TRTEPC9.8-0319C
0.0047(10%) 0.0022(10%) 0.015(10%) 0.15(10%) 0.33(10%) 0.1 0.1 0.1
TB
Varistor
6
10k
NTSEL
D
SGA RXS SGB SGBP SGR RUC VRB VRT
FG
FG
Line activation circuit
HRD
I.430 TTL Interface YTD418 or YTD423
HRD LRD HTD
LRD
HTD
LTD
CLK1536
A1
LTD
CLK1536 RESET
REV
RESET Line activation circuit
10k 10k 10k 10k 10k 10k 10k 10k 10k
11
5
3
TDP RDP ODSEL TSMPSEL MULTI EXID CLKSEL ATEO TEST0,2-9,21,22 TEST1,16-19 TEST10,11,24 TEST28
LPSW LOOP2A CLK200 CLK400 CLK4K CLK192K CLK256K SXA TEST20
AVDD2
1u
Line activation circuit
AVSS2
A2
AVDD1
1u
AVSS1
POWMON LOCAL LPSEL TSMPAUT ATEI TEST12 - 15 TEST23, 25-27
D
A1
DVDD
1u
DVSS
D

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